Sleep control using leakage monitor for Fine-Grain Power Gating

Abstract

We present a sleep control technique using leakage monitor circuit to implement Fine-Grain Power Gating (FGPG). This technique enables us to reduce energy overhead due to sleep control circuits and realize efficient run-time power gating depending on temperature. Furthermore this technique can control the sleep time by changing VREF. We investigated optimization of VREF and energy dissipation by using simulation for microprocessor which applied FGPG.Our technique leads to more reduction of energy dissipation than the conventional sleep control techniques. As compared to non power gating, our technique can reduce the total leakage energy of power-gated function units to 42% at the maximum.