Please use this identifier to cite or link to this item: https://ptsldigital.ukm.my/jspui/handle/123456789/543807
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dc.contributor.authorUsami, Kimiyoshi-
dc.date.accessioned2023-10-25T07:41:47Z-
dc.date.available2023-10-25T07:41:47Z-
dc.identifier.urihttps://ptsldigital.ukm.my/jspui/handle/123456789/543807-
dc.description.abstractPower consumption of LSI chips is one of the biggest concerns in modern computers from smartphones up to high-end servers. In particular, as transistors in integrated circuits get smaller, they become "leaky" and thereby leakage power becomes a major component in the total power dissipation. This paper gives an overview of research activities in my lab to study and develop a dynamic control technique to power on/off execution circuits within a microprocessor chip to reduce leakage power. The technique is composed of novel approaches ranging from the computer architecture level through the circuit level down to the LSI implementation level. Measurement results from fabricated test chips are also demonstrated in the paper.en_US
dc.language.isoenen_US
dc.publisherUniversiti Teknologi Malaysiaen_US
dc.subjectMicroprocessor chipen_US
dc.subjectLarge-scale integration (LSI)en_US
dc.titleResearch on advanced low-power technology of LSI chipsen_US
dc.typeSeminar Papersen_US
dc.format.pages15en_US
dc.identifier.callnoLB2301.S433 2014 semen_US
dc.contributor.conferencename8th SEATUC Symposium-
dc.coverage.conferencelocationUniversiti Teknologi Malaysia-
dc.date.conferencedate2014-03-04-
Appears in Collections:Seminar Papers/ Proceedings / Kertas Kerja Seminar/ Prosiding

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