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Title:	Design and modeling of non-classical silicon-on-insulator metal-semiconductor field effect transistors
Authors:	Hossein Mohammadi (P53283)
Supervisor:	Huda Abdullah, Assoc. Prof. Dr.
Keywords:	Universiti Kebangsaan Malaysia -- Dissertations Dissertations, Academic -- Malaysia Transistors Transistor circuits Semiconductors
Issue Date:	12-Jul-2018
Description:	Silicon-on-insulator metal-semiconductor field effect transistor (SOI-MESFET) has drawn extensive attention in the recent years due to superior high microwave and power electric circuit performances. The downscaling of transistors to attain better electrical performance plays an important role in VLSI technology. The international technology roadmap for semiconductors (ITRS) states the gate length of 10 nm in the year of 2018. The minimum acceptable gate length of SOI-MESFET, which currently is 100 nm, should be shrunk to 10 nm to fulfil ITRS. It is clear that in such dimension, various short channel effects (SCE's) degrade the normal operation of the device. Hence, further downscaling of the device requires innovations in the structure or material. In this research, two new designs of MESFET, the tri-material gate (TMG) SOI-MESFET and the three-gate (TG) SOI-MESFET, are proposed and verified in order to achieve higher level of integration. TMG-MESFET takes advantage of gate-engineering in which the gate consists of three laterally contacting materials with different work functions. Due to this structure, the threshold voltage near the source becomes more positive than that near the drain. Therefore, the carriers in the channel accelerates more and the channel is screened for the variations of drain voltage. So the protection against SCE and drain induced barrier lowering (DIBL) is provided. In TG-MESFET, the channel is surrounded by gate from its three sides to provide closer proximity of gate to the channel. This facilitates better electrostatic control of the channel which results in complete channel inversion, higher current drive, more immunity against SCE, and further scalability. To demonstrate the attributes of the proposed devices, analytical modeling and TCAD simulation are utilized as a tool. Regarding to the results, the slope of potential (ΔΦΔ𝑥⁄) to the drain side which is 1.3 V/μm in classical device reduces to 0.6 V/μm for TMG-MESFET and 0.4 V/μm for TG-MESFET. The threshold voltage roll-off, which appears for channel lengths less than 250 nm in classical SOI-MESFET, becomes considerable in 130 nm for TMG and 50 nm for TG MESFET. For the gate length of 100 nm, DIBL is 200 mV/V for the classical device, 70 mV/V for TMG and 30 mV/V for TG MESFET. This designate the suppression of DIBL in the proposed devices. This study declares the minimum possible gate length of 25 nm for TMG and 10 nm for TG-MESFET which is currently 100 nm for classical device. Thus, the scalability of 10 nm technology node to meet ITRS is obtained.,Ph.D.
Pages:	215
Call Number:	TK7871.9.M634 2018 3 tesis
Publisher:	UKM, Bangi
Appears in Collections:	Faculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina

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