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Title:	Design and implementation of a low-complexity single correlator rake receiver with high-accuracy channel estimation
Authors:	Fazida Hanim Hashim (P33971)
Supervisor:	Masuri Othman, Prof. Dr.
Keywords:	Wireless communication systems Code division multiple access Universiti Kebangsaan Malaysia -- Dissertations Dissertations, Academic -- Malaysia
Issue Date:	16-Apr-2012
Description:	The Code Division Multiple Access (CDMA) Rake receiver collects multipath fading signals and correlates them to get a stronger received signal for signal recovery. One of the major problems of the Rake receiver is its complex architecture, where the arithmetic operations in each Rake correlator, among others, involve the usage of complex multipliers. To get better accuracy in signal recovery, more Rake correlators are required, making the architecture more complex, and consumes more chip area and power. In this thesis, a new low-complexity single correlator Rake receiver with high-accuracy channel estimation is proposed. The focus of this research work is to develop these critical architectures which demonstrate trade-offs between accuracy and complexity, while still meeting the CDMA standards. A software prototype of a conventional Rake receiver in a CDMA multipath environment which consists of a CDMA transmitter, additive white Gaussian noise (AWGN) fading channel, and a Rake receiver is designed and verified in MATLAB. Then three variations of the conventional Rake receiver are proposed: the standard Rake with dominant multipath detector (DMD), single correlator Rake with DMD, and single correlator with DMD and T-Estimate. The proposed main components are then developed at the Register Transfer (RT) level in Verilog, before being simulated and synthesized using ModelSim and Xilinx ISE 8.2i. The hardware components are further optimized by introducing the bit-sign operator and the T-Estimate threshold value for channel estimation. The design is then downloaded to the Virtex-II XC2V500-6-FG456 FPGA board. The implemented design is verified for functionality. When tested in a CDMA environment with different noise factors and multipath components, the software simulation shows that by incorporating the DMD with T-Estimate for a single correlator Rake receiver, the BER can be improved by up to 97.92%. The FPGA hardware synthesis result shows that for the same accuracy, incorporating the efficient computation method for the despreader in the single correlator Rake receiver reduces the number of gates by 51.43%. The Xilinx XST synthesis result shows that the proposed design is operational up to a maximum frequency of 255.069 MHz.,Certification of Master's / Doctoral Thesis" is not available
Pages:	183
Call Number:	TK5103.452.F349 2012 3 tesis
Publisher:	UKM, Bangi
Appears in Collections:	Faculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina

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