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Title:	Design of a flash analog to digital converter for high speed and low power applications
Authors:	Mohammad Jafar Taghizadeh Marvast (P45940)
Supervisor:	Mohd Alauddin Mohd Ali, Prof.
Keywords:	Analog-to-digital converters Analog electronic systems Electronic analog computers Electronic systems Universiti Kebangsaan Malaysia -- Dissertations Dissertations, Academic -- Malaysia
Issue Date:	6-Jul-2012
Description:	Current demand in radar and satellite communications requires high speed and low power flash analog-to-digital converter (ADC). High speed ADC needs a fast comparator, a high-speed encoder, optimized ladder, and a fast sample and hold (S-H) circuit which are equally important. Apart from that, supply voltage, gain, voltage swings, bandwidth, distortion, input offset, linearity, overdrive recovery and other parameters may be significant in the design of flash ADC. In practice, those parameters are not only equally important but also interrelated with each other, thus trade-off between these parameters lead to a multi-dimensional optimization problems. Such trade-off throughout the design process requires intuition and experience to reach an acceptable compromise. Any improvement in flash ADC will significantly improves the current ADC technology. This thesis proposes new design techniques for high speed and low power applications to produce a 4-bit 7 GS/s CMOS high speed flash ADC. Two new comparators are proposed to improve ADC performance. A fully differential comparator consisting of three stages using a new structure (domino CMOS logic) is utilized. Each part of the flash ADC incorporates technique to further improve its performance. In the analog section, ballast capacitance is used to reduce reference voltage deviation at each tap of the reference ladder. This is also an effective technique to reduce thermal noise in the ladder network. Furthermore, an averaging technique is applied to reduce the mismatch impact in comparator arrays. This technique also improves signal-to-noise ratio and static errors induced due to the amplifiers' offset error. Two main contributions of this thesis are the design of high speed and low power comparator which enables the design of a low power and high speed flash ADC. To date, the comparator using CMOS process with the speed of 20 GS/s and comparator utilizing BiCMOS process with the speed of 12.5 GS/s clocked one of the highest speed in the world. The analyses and simulation results were obtained by using 130 nm, 90 nm, 65 nm and 45 nm CMOS technology, SOI process and 120 nm BiCMOS process. Indeed, the flash ADC also achieves lower power consumption compared to earlier designs. The flash ADC is able to operate with 1 V peak-to-peak input range and consume only 18.7 mW. The predicted performance is verified by analyses and simulations using HSPICE tool.,"Certification of Master's/Doctoral Thesis" is not available,Ph.D.
Pages:	102
Call Number:	TK7887.6.M378 2012 3 tesis
Publisher:	UKM, Bangi
Appears in Collections:	Faculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina

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