An investigation of signed bit adder with VHDL

Abstract

Adder is one of the fundamental components of any digital systems. All of the adder-subtractor and multiplier are constructed with adders. The function of adder is to perform an addition process and it is very important especially in digital computer system where the speed of adder will influence the performance of the system itself. Concerning of this matter, this project carried out some simulation to investigate the desired adder. Due to the rapidly growing technology, not only high speed but the usage of hardware needs to be taken into consideration. In this paper, an investigation of Carry Look-ahead Adder (CLA), Ripple Carry Adder (RCA), Carry Select Adder (CSA), and a new scheme adder called Hybird Adder with VHDL will determine the performance of Signed bit adder.