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https://ptsldigital.ukm.my/jspui/handle/123456789/579030| Title: | A programmable cmos delay line for wide |
| Authors: | Bilal I. Abdulrazzaq (UPM) Izhal Abdul Halin (UPM) Lee Lini Roslina M. Sidek (UPM) Nurul Amziah Md. Yunus (UPM) |
| Keywords: | CMOS delay line Synchronous counter Latches Delay element Delay range Duty cycle Linearity PVT variations |
| Issue Date: | Feb-2017 |
| Description: | A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2?s delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous latches has significantly reduced the large occupied active silicon area as well as the huge power consumption. The generated coarse time delay has shown excellent linearity and immunity to PVT variations. The proposed CMOS delay line is designed using a standard 0.13?m Silterra CMOS technology. The active layout area is (101 x 142) ?m2, and the total power consumption is only 0.1 ?W. |
| News Source: | Pertanika Journals |
| ISSN: | 0128-7680 |
| Volume: | 25 |
| Pages: | 123-132 |
| Publisher: | Universiti Putra Malaysia Press |
| Appears in Collections: | Journal Content Pages/ Kandungan Halaman Jurnal |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ukmvital_116404+Source01+Source010.PDF | 1.32 MB | Adobe PDF |  View/Open |
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