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Please use this identifier to cite or link to this item: https://ptsldigital.ukm.my/jspui/handle/123456789/579030
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dc.contributor.authorBilal I. Abdulrazzaq (UPM)
dc.contributor.authorIzhal Abdul Halin (UPM)
dc.contributor.authorLee Lini
dc.contributor.authorRoslina M. Sidek (UPM)
dc.contributor.authorNurul Amziah Md. Yunus (UPM)
dc.date.accessioned2023-11-06T03:12:59Z-
dc.date.available2023-11-06T03:12:59Z-
dc.date.issued2017-02
dc.identifier.issn0128-7680
dc.identifier.otherukmvital:116404
dc.identifier.urihttps://ptsldigital.ukm.my/jspui/handle/123456789/579030-
dc.descriptionA programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2?s delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous latches has significantly reduced the large occupied active silicon area as well as the huge power consumption. The generated coarse time delay has shown excellent linearity and immunity to PVT variations. The proposed CMOS delay line is designed using a standard 0.13?m Silterra CMOS technology. The active layout area is (101 x 142) ?m2, and the total power consumption is only 0.1 ?W.
dc.language.isoen
dc.publisherUniversiti Putra Malaysia Press
dc.relation.haspartPertanika Journals
dc.relation.urihttp://www.pertanika.upm.edu.my/regular_issues.php?jtype=2&journal=JST-25-S-2
dc.rightsUKM
dc.subjectCMOS delay line
dc.subjectSynchronous counter
dc.subjectLatches
dc.subjectDelay element
dc.subjectDelay range
dc.subjectDuty cycle
dc.subjectLinearity
dc.subjectPVT variations
dc.titleA programmable cmos delay line for wide
dc.typeJournal Article
dc.format.volume25
dc.format.pages123-132
dc.format.issueSpecial Issue
Appears in Collections:Journal Content Pages/ Kandungan Halaman Jurnal

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