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Title:	Design of a low power compact CMOS direct conversion receiver for 2.4 GHz RFID applications
Authors:	Mohammad Arif Sobhan Bhuiyan (P64153)
Supervisor:	Mamun Ibne Reaz, Prof. Dr.
Keywords:	Compact CMOS Wireless Metal oxide semiconductors Complementary
Issue Date:	27-Dec-2016
Description:	The demand for low-power wireless devices operating in the 2.4-GHz band has led to extensive research on RF architecture and circuit design. In order to ensure high performance signal processing and data handling in such devices, a low power compact RF receiver is required. Despite of rapid advances in complementary metaloxide semiconductor (CMOS) process, it is still a great challenge for system-on-chip (SOC) designers to achieve this goal. Among the all types of receiver architecture, the direct-conversion receiver (DCR) has been identified as the best suited architecture for the full system integration. The DCR typically comprises of transmit/receive (T/R) switch, low noise amplifier (LNA), down-conversion mixer, bandpass and lowpass filters, variable gain amplifier (VGA) and local oscillator signal generation circuits. Each module has its own constraints such as low isolation and high insertion loss in T/R switch, low gain, low isolation, and high power dissipation in LNA, low conversion gain and high power dissipation in mixer, low bandwidth and low gain in VGA and high phase noise and high power dissipation in LO circuit. The DCR as a whole also suffers from limitations such as flicker noise, DC offset, and high power consumption. The aim of this work is to design a DCR with power consumption at less than 20 mW with die area less than 0.5 mm2. To achieve the aims, parallel resonance and body floated transistors based design of a series-shunt T/R switch, an inductorless design of common gate LNA and a double balanced mixer design have been proposed. Additionally, a three stage differential ring oscillator (DRO) based voltage control oscillator (VCO) has been designed for local oscillator (LO) to obtain large tuning range and low phase noise with optimum power dissipation. The DC offsets, the LO leakage and high power consumption issues in the DCR design have been improved and optimized by the various modifications in other circuits. The proposed circuit for the whole receiver including all individual modules have been simulated using ELDO RF tool of Silterra 0.13-μm standard CMOS process in Mentor Graphics environment. The results obtained from the post-layout simulation show that the T/R switch achieved an insertion loss of 0.85 dB and an isolation of 45 dB; the LNA achieved a gain of 33 dB, a reverse isolation of -33.1dB and a power dissipation of 1.51mW and the mixer circuit achieved a conversion gain of 14.2 dB and a power dissipation of 2 mW. The VGA achieved a gain of 32 dB and a bandwith of >200 MHz and the LO circuit achieved a power dissipation of 8.8 mW. The designed 2.4 GHz DCR in total dissipates 17.2 mW power from a single 1.2V supply voltage. It also shows an overall noise figure of 18.5dB, and occupies an area (without I/O pads) of 0.17 mm2. Compared to recent researches, the proposed DCR dissipates 1.6 mW less power and consumes 0.39 mm2 less chip area. Therefore, the proposed fully integrated DCR will ensure the portability of 2.4 GHz RF devices.,Certification of Master's/Doctoral Thesis" is not available
Pages:	240
Call Number:	TK7871.99.M44B498 2016 3 tesis
Publisher:	UKM, Bangi
Appears in Collections:	Faculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina

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