Please use this identifier to cite or link to this item:
https://ptsldigital.ukm.my/jspui/handle/123456789/457532| Title: | Reka bentuk litar pengesan arus bagi pengujian logik dan IDDQ secara serentak |
| Authors: | Fahmi Samsuri |
| Supervisor: | Robiah Sdidin |
| Keywords: | Iddq testing Integrated circuits - Very large scale integration - Testing Metal oxide semiconductorss Complemantary - Testing |
| Issue Date: | 2002 |
| Call Number: | TK871.99.M44F335 2002 |
| Publisher: | UKM, Bangi |
| Appears in Collections: | Faculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ukmvital_2885+ABSTRACT+ABSTRACT.0.PDF Restricted Access | 5.26 MB | Adobe PDF |  View/Open |
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