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  2. Master Thesis / Tesis Master
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Please use this identifier to cite or link to this item: https://ptsldigital.ukm.my/jspui/handle/123456789/457532
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dc.contributor.advisorRobiah Sdidin
dc.contributor.authorFahmi Samsuri
dc.date.accessioned2023-09-12T09:10:49Z-
dc.date.available2023-09-12T09:10:49Z-
dc.date.issued2002
dc.identifier.otherukmvital:2885
dc.identifier.urihttps://ptsldigital.ukm.my/jspui/handle/123456789/457532-
dc.language.isomay
dc.publisherUKM, Bangi
dc.relationFaculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina
dc.rightsUKM
dc.subjectIddq testing
dc.subjectIntegrated circuits - Very large scale integration - Testing
dc.subjectMetal oxide semiconductorss
dc.subjectComplemantary - Testing
dc.titleReka bentuk litar pengesan arus bagi pengujian logik dan IDDQ secara serentak
dc.typetheses
dc.identifier.callnoTK871.99.M44F335 2002
Appears in Collections:Faculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina

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