Formation of shallower PN junction

Abstract

Sheet resistance of the shallow junctions formed by spin-on-glass diffusion into mono crystalline silicon (mono-silicon) of ultra large scale integration (ULSI) technology was studied using ATHENA and ATLAS's simulator. The junction formation of Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) elevated source/drain structures was made by diffusion from polycrystalline and amorphous silicon layers doped by diffusion from spin on dopants. The diffusion techniques, influence of the microstructure of deposited layers, polysilicon or amorphous silicon to the uniformity of the junction underneath mono-silicon substrate were also studied. Critical thermal budgets required for good shallow P+N, and N+P junction was obtained using rapid thermal annealing of spin on dopant at different temperatures and times. Junctions with depths of 40nm were successfully achieved by the spin on dopant technique. The sheet resistance values were 200 ohm/sq, 44 ohm/sq, 31 ohm/sq and 18 ohm/sq for the temperatures of 850??C, 900??C, 950??C and 1000??C respectively.