Optimization of process parameters for 32nm CMOS device

Husam Ahmed M. Elgomati (P42040)

Please use this identifier to cite or link to this item: https://ptsldigital.ukm.my/jspui/handle/123456789/515021

Full metadata record

DC Field	Value	Language
dc.contributor.advisor	Burhanuddin Yeop Majlis, Prof. Dr.
dc.contributor.author	Husam Ahmed M. Elgomati (P42040)
dc.date.accessioned	2023-10-16T07:53:47Z	-
dc.date.available	2023-10-16T07:53:47Z	-
dc.date.issued	2012-07-20
dc.identifier.other	ukmvital:120401
dc.identifier.uri	https://ptsldigital.ukm.myjspui/handle/123456789/515021	-
dc.description	Minimizing transistor variation through technology optimization and ensuring robust product functionality and performance have always been the important concerns for devices. In this research, we investigate the effects of the process parameters (control factors) variation on response characteristics such as threshold voltage (VTH), leakage current (Ileak) and Source Drain Subthreshold Leakage Current (Ioff) in 32nm MOSFET devices. The setting of process parameters were determined by using orthogonal array of L9 and L18 in Taguchi Method. An orthogonal array, signal-tonoise (S/N) ratio and analysis of variance were employed to study the performance characteristics of the NMOS and PMOS devices. The control factors were used in this research are Gate Oxide Thickness, silicide anneal temperature, VTH implant dose, Poly Thickness, halo implant dose, Source/Drain (S/D) implant dose, compensation implant dose. The fabrication of the transistor device was performed using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. VTH, Ileak and Ioff were used as the evaluation variable. The results were then subjected to the Taguchi method to determine the optimal process parameters and to produce predicted values. In NMOS device, the most dominant or significant factors for S/N Ratio are compensate implant dose and S/D implant dose. For PMOS device, the most dominant or significant factors for S/N Ratio is compensate implant dose. The S/N Ratio values after the optimization approach for arrays L9 and L18 are 34dB and 66dB respectively. In the L9 experiments, the results show that the VTH for NMOS and PMOS devices after optimizations approaches are are +0.10308V at Ileak = 0.1435 μA/μm and -0.10319V at Ileak= 0.1485 μA/μm respectively. For L18 experiments, the VTH for NMOS and PMOS devices are +0.10315V at IOFF=0.6514μA/μm and - 0.1029V at IOFF=0.65129μA/μm respectively. The results obtained are well within ITRS 2009 prediction than our previous L9 and L18 experiment results. As conclusions, setting up design of experiment with the Taguchi Method of L9 and L18 orthogonal arrays and TCAD simulator, the optimal solution for the robust design recipe of 32nm MOSFET devices were successfully achieved.,Certification of Master's / Doctoral Thesis" is not available
dc.language.iso	eng
dc.publisher	UKM, Bangi
dc.relation	Institut Kejuruteraan Mikro dan Nanoelektronik (IMEN) / Institute of Microengineering and Nanoelectronics
dc.rights	UKM
dc.subject	Microelectromechanical systems
dc.subject	Metal oxide semiconductors
dc.subject	Complementary
dc.subject	Universiti Kebangsaan Malaysia -- Dissertations
dc.subject	Dissertations, Academic -- Malaysia
dc.title	Optimization of process parameters for 32nm CMOS device
dc.type	Theses
dc.format.pages	166
dc.identifier.callno	TK7871.99.M44E445 2012 3 tesis
dc.identifier.barcode	005354(2021)(PL2)
Appears in Collections:	Institute of Microengineering and Nanoelectronics / Institut Kejuruteraan Mikro dan Nanoelektronik (IMEN)

Files in This Item:

File	Description	Size	Format
ukmvital_120401+SOURCE1+SOURCE1.0.PDF Restricted Access		1.52 MB	Adobe PDF	View/Open

Show simple item record Recommend this item