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https://ptsldigital.ukm.my/jspui/handle/123456789/487246Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | Fazida Hanim Hashim, Dr. | |
| dc.contributor.author | Pichayan Subramanian Kavitha (P78159) | |
| dc.date.accessioned | 2023-10-11T02:31:09Z | - |
| dc.date.available | 2023-10-11T02:31:09Z | - |
| dc.date.issued | 2022-09-20 | |
| dc.identifier.other | ukmvital:130959 | |
| dc.identifier.uri | https://ptsldigital.ukm.my/jspui/handle/123456789/487246 | - |
| dc.description | Error identification and correction is an essential technique in communication, which enables the transmission of data over an unreliable channel. The current communication channels are highly uncertain and noisy, where errors may be introduced to the input signals which are transmitted from the source to the receiving end. This thesis introduces an efficient implementation of error detection and correction circuit (EDAC) based on a single error signal detection and parity bit precalculation. The core component and its auxiliary components are designed using pass transistor logic. The proposed D flip-flop circuit was designed using a restorable transmission method, which reduced the number of logic components and gave better performance compared to previous circuit designs. The proposed EX-OR circuit is designed using two different combinational logics, which include the and-or-invert method. The schematics and layouts of the proposed error detection and correction circuit and its auxiliary components such as the AND, OR, Comparator, Full adder, D flip-flop and Multiplexer are designed using the Mentor Graphics electronic design tool in the Silterra 0.13 μm technology. Layout versus schematic verification was performed on the modified EDAC circuit, and the simulation results were obtained and compared with the performance of recent circuits. The second error detection and correction (EDAC) method propose a unique circuit that uses arithmetic logic blocks. The Boolean reduction technique was used to design a modified EDAC logic block and its auxiliary components, which reduced one logic gate per block. The modified EDAC circuit simulation results were analyzed and compared with the recent circuit's performance in terms of power dissipation, propagation delay, latency, throughput, and area. The proposed EDAC circuit has improved with other author circuits in terms of power dissipation (94.41%) and high throughput (95.20%). The modified EDAC circuits give 52.910 μW power dissipation, and the throughput of 1.727 GHz. The proposed circuit may be used in the generation communication circuits due to lower power dissipation and reduced chip size.,Ph.D | |
| dc.language.iso | eng | |
| dc.publisher | UKM, Bangi | |
| dc.relation | Faculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina | |
| dc.rights | UKM | |
| dc.subject | Universiti Kebangsaan Malaysia -- Dissertations | |
| dc.subject | Dissertations, Academic -- Malaysia | |
| dc.subject | Error detection | |
| dc.subject | Correction circuit | |
| dc.subject | Internetworking (Telecommunication) | |
| dc.title | Design and layout implementation of an improved error detection and correction circuit using pass transistor logic | |
| dc.type | Theses | |
| dc.format.pages | 148 | |
| Appears in Collections: | Faculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ukmvital_130959+Source01+Source010.PDF Restricted Access | 2.28 MB | Adobe PDF |  View/Open |
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