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Title:	A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM
Authors:	Labonnah Farzana Rahman (P68099)
Supervisor:	Md. Mamun Ibne Reaz, Prof. Dr.
Keywords:	RFID Generator Transponder Voltan Universiti Kebangsaan Malaysia -- Dissertations
Issue Date:	28-Aug-2017
Description:	In analog and digital systems, reducing manufacturing costs and making devices low power, an on-chip high-voltage generator (HVG) is desirable for the embedded nonvolatile memories (NVM) such as electrically erasable programmable read-only memory (EEPROM), Micro-electro-Mechanical Systems (MEMS) device control and power converter switching. The on-die HVG in the standard Complementary Metal-Oxide-Semiconductor (CMOS) processes is very much desirable, since the current topologies choose to design low power and low cost Integrated Circuits (ICs). With the development of radio frequency identification (RFID), embedded EEPROM meets the challenges of high speed, large capacity, high efficiency and especially low power consumption. Therefore, an internal HVG circuit or voltage up converter is widely used in EEPROM due to its high-energy efficiency, small area, low power consumption and low current drivability. Moreover, HVG circuit consumes is the most power hungry module in EEPROM, but it provides a higher voltage than the power supply voltage for programming. Memory programming time, power dissipation, voltage regulation, higher efficiency and the reliability of an EEPROM are strongly influenced by the performance of the HVG circuit. The aim of this research is to design an HVG circuit to meet the requirements of RFID transponder EEPROM. In HVG, charge transfer switched (CTS) based charge pump (CP) is one of the key component, which converts an input voltage to a boosted output voltage higher than the power supply voltage (VPP). However, the major disadvantage of the CP circuit is the pumping efficiency decreases as the number of stages increases due to large ripple voltages. Nevertheless, in EEPROM a large portion of the total power is consumed by HVG circuit, which needs to design properly to meet the demands. Therefore, a regulator circuit consists of the voltage divider, comparator and a voltage reference, which are required to reduce ripple voltage, increase pumping efficiency and decreased power dissipation of the HVG. On the other hand, a clock driving circuit consists of the current-starved ring oscillator (CSRO) and the non-overlapping clock generator (NOC_GEN) is required to drive the clock signals of the HVG circuit. In this research, Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed the designed CSRO dissipates only 4.9 μW with the frequency of 10.2 MHz and the phase noise is only -119.38 dBc/Hz@1MHz. Moreover, the proposed CP circuit is able to generate maximum 13.53 V as VPP and dissipated only 31.01 μW power under 1.8 V of input power supply voltage (VDD), which is better than recent researches. After integrating all the HVG modules, the results showed that the regulated HVG circuit is also able to generate higher VPP of 14.59 V, while the total power dissipated is only 0.12 mW with lower chip area of 0.044 mm2. Moreover, the HVG circuit produces higher pumping efficiency of 90% while reduces the ripple voltage to less than 4 mV. Therefore, the integration of all the proposed modules in HVG ensured low ripple programming voltages, higher pumping efficiency and low power dissipated EEPROM, which can be extensively used in low power applications such as NVM, RFID transponder, on-chip DC-DC converter and other low power applications.,Certification of Master's/Doctoral Thesis" is not available
Pages:	151
Publisher:	UKM, Bangi
Appears in Collections:	Faculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina

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