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Title:	The design and fabrication of low power sense amplifier and charge pump circuits for readerless RFID transponder
Authors:	Labonnah Farzana Rahman (P52906)
Supervisor:	Mohd. Alauddin Mohd. Ali, Prof. Dr.
Keywords:	Radio frequency identification systems -- Design and construction Radio frequency identification systems Universiti Kebangsaan Malaysia -- Dissertations Dissertations, Academic -- Malaysia
Issue Date:	21-Jul-2012
Description:	The use of Radio Frequency Identification (RFID) applications is still limited due to high implementation cost of the RFID reader, limited address space of the transponder and local mobility. Instead of the costly reader, a robust Wireless Network Interface Card (WNIC) can be used to communicate with the transponder. However, the memory block, which is one of the major parts in RFID transponder, has to be redesigned. Among non-volatile-memories (NVM), Electrically Erasable Programmable Read Only Memory (EEPROM) is the most suitable memory type used for an RFID transponder. The main objective of this research work is to design and develop improved CMOS Sense Amplifier (SA) and Charge Pump (CP) circuits, which are compatible for readerless RFID transponder EEPROM. Memory read access time; power dissipation and the reliability of an EEPROM are strongly influenced by the performance of the SA. Voltage type SA is the key element for sensing/reading process in EEPROM and suitable for low voltage applications. Moreover, to reduce the continuous power supply in integrated circuits, CP circuit is widely used to direct charge flow and to generate boosted output voltage higher than the power supply voltage (VDD) in EEPROM. In this research the CP, circuit is designed by using a charge transfer switch (CTS) to reduce the extra power dissipation, threshold voltage loss and the parasitic capacitance. The SA is designed to work in low voltage while the CP is designed for achieving low power, free from threshold voltage loss and parasitic capacitance effect. Row decoder and the clock generator circuits are also designed to support these two main blocks of the RFID transponder EEPROM. Mentor Graphics EldoSpice software package is used to simulate the circuitry. The clock generator module is designed to obtain nonoverlapping clock signals for the CP circuit, which boosts up the output voltage. As a result, the continuous power supply is reduced. The entire design of the row decoder, SA and clock generator are based on 0.18-µm CMOS process with one poly and two metal layers. Simulation results showed that the voltage type SA circuit is capable of working in low voltages (1V, 2.6V) with more consistency than previous research works. The simulated output of the proposed CP circuit showed that it is able to generate minimum 5.62V to maximum 10.29V output voltages under different VDD (1.8V and 3.3V) respectively, which are higher than previous research works. Moreover, the CP circuit power dissipation (178.10 µW) is much less than the other research works. Therefore, the design of the SA and the CP circuits are better suited for low power read and write operation in EEPROM, which will be compatible with the readerless RFID transponder.,Certification of Master's / Doctoral Thesis" is not available
Pages:	125
Call Number:	TK6570.I34R337 2012 3 tesis
Publisher:	UKM, Bangi
Appears in Collections:	Faculty of Engineering and Built Environment / Fakulti Kejuruteraan dan Alam Bina

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